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INTEGRATED CIRCUITS
DATA SHEET
UMA1005T Dual low-power frequency synthesizer
Preliminary specification Supersedes data of September 1992 File under Integrated Circuits, IC03 November 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
FEATURES * Fast locking by `Fractional-N' divider * Auxiliary synthesizer * Digital phase comparator with proportional and integral charge pump output * High-speed serial input * Low-power consumption * Programmable charge pump currents * Supply voltage range 2.9 to 5.5 V. APPLICATIONS * Mobile telephony * Portable battery-powered radio equipment. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UMA1005T SSOP20 DESCRIPTION GENERAL DESCRIPTION
UMA1005T
The UMA1005T is a low-power, high-performance dual frequency synthesizer fabricated in CMOS technology. Fractional-N division with selectable modulo 5 or 8 is implemented in the main synthesizer. The detectors and charge pumps are designated to achieve 10 to 5000 kHz channel spacing using fractional-N decreases the channel spacing by a factor 5 or 8. Together with an external standard 2, 3 or 4 ratio prescaler the main synthesizer can operate in the GHz frequency range. Channel selection and programming is realized by a high-speed 3-wire serial interface.
VERSION SOT266-1
plastic shrink small outline package; 20 leads; body width 4.4 mm
November 1994
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Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
BLOCK DIAGRAM
UMA1005T
/1 page = 296 mm (Datasheet) 4 DATA 5 CLOCK 6 STROBE
27 mm
SERIAL INPUT + PROGRAM LATCHES
EM 2 INM1 INM2 3
PR 2
NM1 12
NM2 NM3 8
NM4 4
FMOD
NF 3 PRESCALER FEEDBACK CN 8 NORMAL OUTPUT CHARGE PUMP CL 13 SPEED-UP OUTPUT CHARGE PUMP CK PHP 15 18 19 16 FB1 FB2 RF RN
MAIN DIVIDERS
FRACTIONAL ACCUMULATOR FRD
EM MAIN PHASE DETECTOR
2
UMA1005T
SM 2 NR EM + EA 7 12 REFERENCE DIVIDER SA 2 AUXILIARY REFERENCE SELECT 2 2 2 2 MAIN REFERENCE SELECT
2
INR
4 INTEGRAL OUTPUT CHARGE PUMP 11 PHI
9 AUXILIARY OUTPUT CHARGE PUMP
RA
EA PA EA 8 INA 41 AUXILIARY DIVIDER 1 V DDD NA 12 AUXILIARY PHASE DETECTOR
10
PHA
17
LOCK
14 V DDA
20 V SS
12 V SSA
MEA668 - 1
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
PINNING SYMBOL PIN VDDD INM1 INM2 DATA CLOCK STROBE INR INA RA PHA PHI VSSA PHP VDDA RN RF LOCK FB1 FB2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION digital supply voltage main divider positive input; rising edge active main divider negative input; falling edge active serial data input line serial clock input line serial strobe input line reference divider input line; rising edge active auxiliary divider input line; rising edge active auxiliary current setting; resistor to VSS auxiliary phase detector output integral phase detector output analog ground; internally connected to VSS proportional phase detector output analog supply voltage main current setting input; resistor to VSS fractional compensation current setting input; resistor to VSS lock detector output feedback output 1 for prescaler modulus control feedback output 2 for prescaler modulus control common ground connection
INM2 DATA CLOCK STROBE INR INA RA 3 4 5 UMA1005T 6 7 8 9 15 14 13 12 11
MEA667
UMA1005T
1/2 page (Datasheet) V DDD
INM1
1 2
20 V SS 19 18 17 16 FB2 FB1 LOCK RF RN V DDA PHP V SSA PHI
22 mm
PHA 10
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
FUNCTIONAL DESCRIPTION Serial programming input The serial input is a 3-wire input (CLOCK, STROBE and DATA) to program all counter ratios, DACs, selection and enable bits. The programming data is structured into 24 or 32-bit words. Each word includes 1 or 4 address bits. Figure 3 shows the timing diagram of the serial input. When the STROBE = LOW, the clock driver is enabled and on the positive edges of the CLOCK the signal on the DATA input is clocked into a shift register. When the STROBE = HIGH, the clock is disabled and the data in the shift register remains stable. Depending on the 1 or 4 address bits the data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 4 words must be sent: 1. D word. 2. C word. 3. B word. 4. A word. Figure 4 shows the format and the contents of each word. The E word is for testing purposes only. The E (test) word
UMA1005T
is reset when programming the D word. The data for NM4, CN and PR is stored by the B word temporary registers. When the A word is loaded, the data of these temporary registers is loaded together with the A word into the work registers which avoids false temporary main divider input. CN is only loaded from the temporary registers when a short 24-bit A0 word is used. CN will be directly loaded by programming a long 32-bit A1 word. The flag LONG in the D word determines whether A0 (LONG = 0) or A1 (LONG = 1) format is applicable. The A word contains new data for the main divider. The A word is loaded only when a main divider synchronization signal is also active, to avoid phase jumps when reprogramming the main divider. The synchronization signal is generated by the main divider. It disables the loading of the A word each main divider cycle during maximum 300 main divider input cycles. To make sure that the A word will be correctly loaded the STROBE signal must be HIGH for at least 300 main divider input cycles. Programming the A word also means that the main charge pumps on outputs PHP and PHI are set into the speed-up mode as long as the STROBE remains HIGH.
handbook, full pagewidth
data valid
data change VH
DATA
D0 t suDA t hDA
D1
D30 t HC
D31 VL t LC VH
CLOCK VL t suST STROBE VL clock enabled shift in data clock disabled store data
MBE121
t hST VH
Fig.3 Serial input timing sequence.
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Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
andbook, full pagewidth MSB
LSB D0 NF NM1 NM2 NM3 NM2 CN
word D31 A1 0
D23 A0 0 NF NM1 NM2 NM3 NM2
D0 PR = `01' PR `01'
B
1
0
0
0
NM4
CN
CK
CL
PR
C
1
0
0
1
0
0
0
NA
PA
D
1
0
1
0
0
0
0
NR
SM
EM
SA
F EA M O D
L O N G
E
1 D23
1
1
1
TEST BITS D0
MBE122
address bits
Fig.4 Serial input word format.
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Preliminary specification
Dual low-power frequency synthesizer
Table 1 Description of symbols used in Fig.4 BITS(1) 12 8 if PR = 01 4 if PR 01 NM3 NM4 PR 4 if PR = 1X 4 if PR = 11 or 00 2 FUNCTION
UMA1005T
SYMBOL NM1 NM2
number of main divider cycles when prescaler is programmed in ratio R1 (FB1 = 1; FB2 = 0); note 2 number of main divider cycles when prescaler is programmed in ratio R2 (FB1 = 0; FB2 = 0); note 2 number of main divider cycles when prescaler is programmed in ratio R3 (FB1 = 0; FB2 = 1); note 2 number of main divider cycles when prescaler is programmed in ratio R4 (FB1 = 1; FB2 = 1); note 2 prescaler type in use: PR = 01; modulus 2 prescaler PR = 10; modulus 3 prescaler PR = 11; modulus 4 prescaler PR = 00; modulus 4 prescaler (inhibit ratio 3)
NF FMOD
3 1
fractional-N increment fraction-N modulus selection flag: 1 = modulo 8 0 = modulo 5
LONG
1
A word format selection flag: 0 = 24-bit A0 format 1 = 32-bit A1 format
CN CL CK EM EA SM SA NR NA PA
8 2 4 1 1 2 2 9 9 1
binary current setting factor for main charge pumps binary acceleration factor for proportional charge pump current binary acceleration factor for integral charge pump current main divider enable flag auxiliary divider enable flag reference select for main phase detector reference select for auxiliary phase detector reference divider ratio auxiliary divider ratio auxiliary prescaler mode: PA = 0; divide-by-4 PA = 1; divide-by-1
Notes 1. X = don't care. 2. Not including reset cycles and fractional-N effects. Auxiliary variable divider The input signal on INA is amplified to a logic level by a single ended input buffer, which accepts LOW level AC coupled input signals. This input stage is enabled if the serial control bit EA = 1. Disabling means that all currents November 1994 7 in the input stage are switched off. A fixed divide by 4 is enabled if PA = 0. This divider has been optimized to accept a high-frequency (90 MHz at a supply voltage range of 4.75 to 5.5 V) input signal. If PA = 1 this divider is disabled and the input signal is fed directly to the second
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
stage, which is a 9-bit programmable divider with standard input frequency (30 MHz). The division ratio can be expressed as: If PA = 0; N = 4 x NA. If PA = 1; N = NA; with NA = 4 to 511. Reference variable divider (Fig.5) The input signal on INR is amplified to a logic level by a single ended input buffer, which accepts LOW level AC coupled input signals. This input stage is enabled by the OR function of the serial input bits EA and EM. Disabling means that all currents in the input stage are switched off. The reference divider consists of a programmable divider by NR (NR = 4 to 511) followed by a 3-bit binary counter. The 2-bit SM determines which of the 4 output pulses is selected as main phase detector input. The 2-bit SA determines the selection of the auxiliary phase detector signal. To obtain the best time spacing for the main and
UMA1005T
auxiliary reference signals, the opposite output will be used for the auxiliary phase detector, reducing the possibility of unwanted interactions. For this reason the programmable divider produces a symmetric output pulse for even ratios and a 1 input cycle asymmetric pulse for odd ratios. Main variable divider The input signals on INM1 and INM2 are amplified to a logic level by a balanced input comparator giving a common mode rejection. This input stage is enabled when serial control bit EM = 1. Disabling means that all currents in the comparator are switched off. The main divider is built-up by a 12-bit counter plus a sign bit. Depending on the serial input values of NM1, NM2, NM3, NM4 and the prescaler select PR, the counter will select a prescaler ratio during a number of input cycles in accordance with the information in Table 2.
book, full pagewidth
MAIN SELECT SM = `00' SM = `01' SM = `10' SM = `11' reference input main phase detector
divide by NR
2
2
2 AUXILIARY SELECT SA = `11' SA = `10' SA = `01' auxiliary phase detector
MBE123
SA = `00'
Fig.5 Reference variable divider.
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Preliminary specification
Dual low-power frequency synthesizer
Table 2 Selection of prescaler ratio FB1 1 1 0 0 0 1 FB2 0 0 0 0 1 1 R1 R1(2) R2 R2(2) R3; if PR = 1X R4; if PR = 11 or 00
UMA1005T
COUNTER STATUS (-NM1 - 1) to 0 (-NM1 - 1) to -1 1 to NM2 0 to NM2 0 to NM3 0 to NM4 Notes 1. X = don't care.
PRESCALER RATIO(1)
2. When the fractional accumulator overflows. The total division ratio from prescaler to the phase detector expressions are given in Table 3. Table 3 Total division from prescaler to phase detector expressions EXPRESSION N = (NM1 + 2) x R1 + NM2 x R2 N = (NM1 + 1) x R1 + (NM2 + 1) x R2; note 1 PR = 10 PR = 11 PR = 00 N = (NM1 + 2) x R1 + NM2 x R2 + (NM3 + 1) x R3 N = (NM1 + 1) x R1 + (NM2 + 1) x R2 + (NM3 + 1) x R3; note 1 N = (NM1 + 2) x R1 + NM2 x R2 + (NM3 + 1) x R3 + (NM4 + 1) x R4 N = (NM1 + 1) x R1 + (NM2 + 1) x R2 + (NM3 + 1) x R3 + (NM4 + 1) x R4; note 1 N = (NM1 + 2) x R1 + NM2 x R2 + (NM4 + 1) x R4 N = (NM1 + 1) x R1 + (NM2 + 1) x R2 + (NM4 + 1) x R4; note 1 Note 1. When the fractional accumulator overflows. When the prescaler ratio is R2 = R1 + 1 the total division ratio N = N + 1. Table 4 Modulus prescaler BIT CAPACITY PR 00 01 10 11 MODULUS PRESCALER NM1 4 2 3 4 12 12 12 12 NM2 4 8 4 4 NM3 - - 4 4 NM4 4 - - 4
CONDITION PR = 01
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Preliminary specification
Dual low-power frequency synthesizer
The loading of the work registers NM1, NM2, NM3, NM4 and PR is synchronized with the state of the main counter, to avoid extra phase disturbance when switching over to another main divider ratio as is explained in Section "Serial programming input". At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also the fractional accumulator is incremented with NF. The accumulator works modulo Q. Q is preset by the serial control bit FMOD to 8 when FMOD = 1. Each time the accumulator overflows, the feedback to the prescaler will select one cycle using prescaler ratio R2 instead of R1. As shown above, this will increase the overall division ratio by 1 if R2 = R1 + 1. The mean division ratio over Q main NF divider cycles will then be: NQ = N + ------Q Programming a fraction means the prescaler with main divider will divide by N or N + 1. The output of the main divider will be modulated with a fractional phase ripple. This phase ripple is proportional to the contents of the fractional accumulator FRD, which is used for fractional current compensation. Phase detectors (Fig.6) The auxiliary and main phase detectors are a 2 D-type flip-flop phase and frequency detector. The flip-flops are set by the negative edges of output signals of the dividers. The reset inputs are activated when both flip-flops have been set and when the reset enable signal is active (LOW). Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or dead band around zero phase error. The flip-flops drive on-chip charge pumps. A pull-up current from the charge pump indicates that the VCO frequency shall be increased while a pull-down pulse indicates that the VCO frequency shall be decreased. Current settings The UMA1005T has 3 current setting pins RA, RN and RF. The active charge pump currents and the fractional compensation currents are linearly dependent on the current in the current setting pins. This current IR can be set by an external resistor to be connected between the current setting pin (pin 9) and VSS. The typical value for R (current setting resistor) can be calculated with the equation: ( V DDA - 0.5 ) - 237 I R R = -----------------------------------------------------------IR
UMA1005T
The current can be set to zero by connecting the corresponding pin to VDDA. Auxiliary output charge pumps The auxiliary charge pumps on pin PHA are driven by the auxiliary phase detector and the current value is determined by the external resistor (Rext) at pin RA. The active charge pump current is typically: |IPHA| = 8 x IRA. Main output charge pumps and fractional compensation currents The main charge pumps on pins PHP and PHI are driven by the main phase detector and the current value is determined by the current at pin RN and via a number of DACs which are driven by registers of the serial input. The fractional compensation current is determined by the current at pin RF, the contents of the fractional accumulator FRD and a number of DACs driven by registers from the serial input. The timing for the fractional compensation is derived from the reference divider. The current is on during 1 input reference cycle before and 1 cycle after the output signal to the phase comparator. Figure 7 shows the waveforms for a typical case. When the serial input A word is loaded, the output circuits are in the `speed-up mode' as long as the STROBE is HIGH, else the `normal mode' is active. NORMAL MODE In the `normal mode' the current output at PHP is: IPHP(N) = Ipump10 + Icomp10. Where: CN x I RN I pump10 = ----------------------- ; charge pump current. 29 FRD x I RF I comp10 = --------------------------- ; fractional compensation current. 128 In `normal mode' the current at output PHI is zero.
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Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
handbook, full pagewidth
L `1' INR REFERENCE DIVIDER R D C VDDA R P R AUXILIARY AND MAIN DIVIDER `1' X D C Q N V SSA N-type charge pump P-type charge pump PH Q
INR
L
R
X
P
N
PH
MBE124
Fig.6 Phase detector structure with timing.
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Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
SPEED-UP MODE In `speed-up mode' the current in output PHP is: IPHP(S) = IPHP(N) + Ipump11 + Icomp11. Where: Ipump11 = Ipump10 x 2(CL + 1); charge pump current. Icomp11 = Icomp10 x 2(CL + 1); fractional compensation current. In `speed-up mode' the current in output PHI is: IPHI(S) = Ipump21 + Icomp21. Where: Ipump21 = Ipump11 x CK; charge pump current. Icomp21 = Icomp11 x CK; fractional compensation current. Figure 7 shows that for a proper fractional compensation the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. This means that the current setting on the inputs RN and RF I RN 29 x Q x f VCO must have following ratio: ------- = ------------------------------------------------ . I RF 64 x CN x f i ( max ) 2 Where: Q = fractional-N modulus. fVCO = fi(max)1 x N; input frequency of the prescaler. fi(max)1 = maximum input frequency of the main divider (pins INM1 and INM2). fi(max)2 = maximum input frequency of the reference divider (pin INR). Lock detect The output LOCK is HIGH when the auxiliary phase detector and the main phase detector indicate a lock condition. The lock condition is defined as a phase difference of less than 1 cycle on the reference input INR. The lock condition is also fulfilled when the relative counter is disabled (EM = 0 or EA = 0 respectively) for the main or auxiliary counter respectively.
UMA1005T
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Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
handbook, full pagewidth INR
INM N N N1 N N1
detector output
contents accumulator
2
4
1
3
0
fractional compensation current
pulse-width modulation outputs PHP and PHI
mA t1 A t2
pulse-level modulation
MBE125
Fig.7 Waveforms for NF = 2 and fraction = 0.4.
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Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA VI In Ptot Tstg Tamb digital supply voltage analog supply voltage voltage on any input DC current into any input or output total power dissipation storage temperature operating ambient temperature PARAMETER MIN. -0.5 -0.5 -0.5 -10 - -65 -40
UMA1005T
MAX. 6.5 6.5 +10 25 +150 +70 V V
UNIT
VDD + 0.5 V mA mW C C
DC CHARACTERISTICS VDDD = VDDA = 2.9 to 5.5 V; Tamb = -40 to +70 C; unless otherwise specified. SYMBOL Supply IDDD(stb) IDDD IDDA(stb) IDDA digital standby supply current operating digital supply current analog standby supply current operating analog supply current EM = EA = 0; inputs on VDD or 0 note 1 VRA = VDDA; VRF = VDDA; VRN = VDDA note 1 - - - - - - - - 5 5 10 0.6 A mA A mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital inputs CLK, DATA and STROBE VIH VIL VOL VOH IPHA HIGH level input voltage LOW level input voltage 0.7VDD 0 - VDD - 0.4 400 160 - - - - - - VDD 0.3VDD 0.4 - V V
Digital outputs FB1, FB2 and LOCK LOW level output voltage HIGH level output voltage IO = 2 mA; note 2 IO = -2 mA; note 2 IRA = -62.5 A; VPHA = 12VDD; note 2 IRA = -25 A; VPHA = 12VDD I PHA --------------I PHA IPHA M relative output current variation output current matching IRA = -62.5 A; notes 2 and 3 IRA = -62.5 A; VPHA = 12VDD; notes 2 and 4 V V A A %
Charge pump PHA output current 500 200 2 600 240 6
-
50
A
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Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Charge pump PHP; normal mode (notes 5, 6 and 7); VRF = VDD IPHP(N) output current IRN = -62.5 A; VPHP = 12VDD; note 2 IRN = -25 A; VPHP = 12VDD IPHP(N) relative output current variation IRN = -62.5 A; note 3 IRN = -62.5 A; VPHP = 12VDD; notes 2 and 4 IRN = -62.5 A; VPHP = 12VDD; note 2 IRN = -25 A; VPHP = 12VDD IPHP(S) IPHP(S M) relative output current variation output current matching IRN = -62.5 A; notes 2 and 3 IRN = -62.5 A; VPHP = 12VDD; notes 2 and 4 IRN = -62.5 A; VPHI = 12VDD; note 2 IRN = -25 A; VPHI = 12VDD IPHI(S) IPHI(S M) relative output current variation output current matching IRN = -62.5 A; notes 2 and 3 440 175 - - 550 220 2 - 660 265 6 50 A A % A
IPHP(N M) output current matching
Charge pump PHP; speed-up mode (notes 5, 6 and 8); VRF = VDD IPHP(S) output current 2.20 0.85 - - 2.75 1.1 2 - 3.30 1.35 6 250 mA mA % A
Charge pump PHI; speed-up mode (notes 5, 6 and 9); VRF = VDD IPHI(S) output current 4.4 1.75 - 5.5 2.2 2 - 6.6 2.65 8 500 mA mA % A
IRN = -62.5 A; - VPHI = 12VDD; notes 2 and 4 IRF = -62.5 A; FRD = 1 to 7; notes 2 and 12 IRF = -25 A; FRD = 1 to 7; note 12 -675
Fractional compensation PHP; normal mode (notes 5, 10 and 11); VRN = VDD; VPHP = 12VDD IPHP(F N) fractional compensation output current PHP as a function of FRD -500 -325 nA
-270
-200
-130
nA
Fractional compensation PHP; speed-up mode (notes 5, 11 and 13); VRN = VDD; VPHP = 12VDD IPHP(F S) fractional compensation output current PHP as a function of FRD IRN = -62.5 A; FRD = 1 to 7; notes 2 and 12 IRN = -25 A; FRD = 1 to 7; note 12 -3.35 -2.50 -1.65 A
-1.35
-1.00
-0.65
A
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Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fractional compensation PHI; speed-up mode (notes 5, 11 and 14); VRN = VDD; VPHP = 12VDD IPHI(F) fractional compensation output current PHI as a function of FRD IRN = -62.5 A; FRD = 1 to 7; notes 2 and 12 IRN = -25 A; FRD = 1 to 7; note 12 Charge pump leakage currents; charge pump not active IPHP(LO) output leakage current PHP normal mode; VPHP = 0.7 to VDDA - 0.8 V note 5 output leakage current PHI normal mode; VPHI = 0.7 to VDDA - 0.8 V note 5 - 10 750 nA -5.4 -4.0 -2.6 A
-2.15
-1.60
-1.05
A
IPHI(LO)
-
10
100
nA
IPHA(LO) Notes
output leakage current PHA VPHA = 0.7 to VDDA - 0.8 V
-
10
750
nA
1. Operational conditions: a) Main and auxiliary divider enabled (EM = EA = 1). b) NA = 125. c) NR = 125. d) NM1 = 60. e) NM2 = 63. f) fi(max)1 = fi(max)2 = 15 MHz. g) fi(max)3 = 60 MHz. h) Lock condition. i) Normal mode; note 5 j) IRN = IRF = IRA = 25 A. k) CN = 255. l) PA = 0. 2. Limited supply voltage range 4.5 to 5.5 V. 3. The relative output current variation is defined as: I2 - I1 I O -------- = 2 x ----------------- ; with V1 = 0.7 V; V2 = VDD - 0.8 V (see Fig.8). I2 + I1 IO 4. The output current matching is measured when both (positive and negative current) sections of the output charge pumps are on. 5. When a serial `A' word is programmed, the main charge pumps on PHP and PHI are in the `speed-up mode' as long as STROBE = HIGH, otherwise the main charge pumps are in the `normal mode'. 6. Monotonicity is guaranteed with CN = 0 to 255. CN 7. Typical output current: I PHP(N) = - I RN x -------- ; specification condition: CN = 255. 29
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Preliminary specification
Dual low-power frequency synthesizer
( CL + 1 )
UMA1005T
2 +1 8. Typical output current: I PHP(S) = - I RN x CN x ------------------------------- ; specification conditions: 29 a) CN = 255; CL = 1 or, b) CN = 75; CL = 3. 9. Typical output current: I PHI = - I RN x CN x 2 a) CN = 160; CL = 3; CK = 1 or, b) CN = 160; CL = 2; CK = 2 or, c) CN = 160; CL = 1; CK = 4 or, d) CN = 160; CL = 0; CK = 8. FRD 10. Typical fractional compensation output current: I PHP(F N) = I RF x ------------ ; specification condition: FRD = 1 to 7. 128 11. The compensation current specified does not include the leakage current of this output. 12. FRD is the value of the 3-bit fractional accumulator. 2 +1 13. Typical fractional compensation output current: I PHP(F S) = I RF x FRD x ------------------------------- ; specification conditions: 128 FRD = 1 to 7; CL = 1. 14. Typical fractional compensation output current: I PHI(F) = I RF x FRD x 2 a) FRD = 1 to 7; CL = 1; CK = 2 or, b) FRD = 1 to 7; CL = 2; CK = 1.
( CL + 1 ) ( CL + 1 ) ( CL + 1 )
CK x -------- ; specification conditions: 29
CK x --------- ; specification conditions: 128
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Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
handbook, full pagewidth
Io I2 I1
V1
V2
Vo
I2 I1
MBE126
Fig.8 Relative output current variation.
AC CHARACTERISTICS VDDD = VDDA = 2.9 to 5.5 V; Tamb = -40 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - TYP. - - - MAX. UNIT
Main divider (inputs INM1 and INM2) fi(max)1 VINM(p-p) maximum input frequency note 1 differential input signal amplitude VINM1 - VINM2 (peak-to-peak value) common mode range for VINM1 and VINM2 propagation delay time from INM1 and INM2 to FB1 and FB2 mark-to-space ratio for differential input signals minimum input impedance resistive; note 2 capacitive; note 2 note 1 10 30 600 MHz MHz mV
VCM tpd
1 - - 35 : 65 5 -
- - 18 - - -
VDD - 1 60 30 65 : 35 - 5
V ns ns
msr Zi(min)
k pF
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Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
SYMBOL
PARAMETER
CONDITIONS
MIN. - - -
TYP. - - -
MAX.
UNIT
Reference divider (input INR) fi(max)2 Vi(p-p) maximum input frequency note 1 input signal amplitude AC coupled (peak-to-peak value) minimum input impedance resistive; note 2 capacitive; note 2 Auxiliary divider (input INA) fi(max)3 maximum input frequency prescaler enabled; PA = 0 prescaler enabled; PA = 0; note 1 prescaler disabled; PA = 1 prescaler disabled; PA = 1; note 1 Vi(p-p) input signal amplitude AC coupled (peak-to-peak value) minimum input impedance resistive; note 2 capacitive; note 2 Serial interface (inputs DATA, CLOCK and STROBE); see Fig.3 fclk tHC tLC tsuDA thDA tsuST thST Notes 1. Limited supply voltage range 4.5 to 5.5 V. 2. Periodically sampled; not 100% tested. clock frequency clock HIGH time clock LOW time DATA set-up time DATA hold time STROBE set-up time STROBE hold time - 30 30 30 30 30 30 - - - - - - - 10 - - - - - - MHz ns ns ns ns ns ns 35 90 15 30 300 - - - - - - - - - - MHz MHz MHz MHz mV 15 30 300 MHz MHz mV
Zi(min)
5 -
- -
- 5
k pF
Zi(min)
5 -
- -
- 5
k pF
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Preliminary specification
Dual low-power frequency synthesizer
PACKAGE OUTLINE
UMA1005T
handbook, full pagewidth
6.75 6.40
4.5 4.3
A
S 0.6 (4x) 0.2
0.1 S
6.6 6.2
20
11 1.4 1.2
0.6 0.5 0.15 0 0.20 0.13 1.5 1.2
pin 1 index 1 10 detail A 0.32 0.20 0.13 M (20x) 0.8 0.3
0 to 10o
MBC237 - 1
0.65
Dimensions in mm.
Fig.9 Plastic shrink small outline package; 20 leads; body width 4.4 mm (SSOP20; SOT266-1).
November 1994
20
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
SOLDERING Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
UMA1005T
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
November 1994
21
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
NOTES
UMA1005T
November 1994
22
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
NOTES
UMA1005T
November 1994
23
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors LTD., 276 Bath road, Hayes, MIDDLESEX UB3 5BX, Tel. (081)73050000, Fax. (081)7548421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD35 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
413061/1500/02/pp24 Document order number: Date of release: November 1994 9397 743 40011
Philips Semiconductors

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